Nonvolatile semiconductor storage device equipped with a comparison buffer for reducing power consumption during write

ABSTRACT

A semiconductor storage device includes plural bit lines and plural word lines. The memory cell array has plural memory cells that are connected with the bit lines and word lines, and can store data. Plural sense amplifiers detect the data stored in the memory cells. Plural write drivers write data in the memory cells. A comparison buffer temporarily stores the write data to be written in the memory cells by the write driver. In a series of write sequences, the comparison buffer stores the read data from the memory cells selected as the write object and the write data to be written in the selected memory cells. After a series of write sequences, when the pre-charge command for resetting the voltage of the bit lines is received, the write execution command is executed so that the comparison buffer executes write in the selected memory cells.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority fromJapanese Patent Application No. 2012-006321, filed Jan. 16, 2012; theentire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate to a semiconductor storage device.

BACKGROUND

MRAM (magnetic RAM) and other nonvolatile memories have been developedas substitutes of DRAM (dynamic random access memory) and other volatilememories.

However, for MRAM, because data are written as current flows in MTJ(magnetic tunnel junction) elements, it takes some time to perform awrite operation. Consequently, when the memory cells belonging to thesame bank are repeatedly accessed over a short time period, it may notbe possible to carry out a data write.

In addition, when a data write is carried out, if the logic of the dataalready stored in the memory cells is identical to the logic of the datato be written the write current (cell current) used to overwriteexisting data with the new data is wastefully used.

DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating a memory cell array of an MRAMand its peripheral circuit according to a first embodiment.

FIG. 2 is a diagram illustrating the components and operation of asingle memory cell MC.

FIG. 3 is a diagram illustrating the connection relationship between aread global data bus RGDB as well as a write global data bus WGDB andmemory cell macros MCM1 through MCM4.

FIG. 4 is a block diagram illustrating the internal components of acomparison buffer CMPB.

FIG. 5 is a time diagram illustrating a data write operation of thememory of the first embodiment.

FIG. 6 is a block diagram illustrating the components of an MRAMaccording to a second embodiment.

FIG. 7 is a time diagram illustrating a data write operation of thememory of the second embodiment.

FIG. 8 is a block diagram illustrating the components of an MRAMaccording to a third embodiment.

FIG. 9 is a block diagram illustrating the components of a comparisonbuffer CMPB according to the third embodiment.

FIG. 10 is a block diagram illustrating the components of an MRAMaccording to a fourth embodiment.

FIG. 11 is a block diagram illustrating the components of an MRAMaccording to a fifth embodiment.

FIG. 12 is a block diagram illustrating the components of a comparisonbuffer CMPB according to the fifth embodiment.

DETAILED DESCRIPTION

In general, example embodiments will be explained with reference tofigures. However, the invention is not limited to these embodiments.

According to an embodiment, there is provided a semiconductor storagedevice that can carry out data writes continuously while reducing thewasteful power consumption during the data write operation.

The semiconductor storage device according to the present embodiment hasplural bit lines and plural word lines. The memory cell array has pluralmemory cells that can store data and are connected to the bit lines andword lines. Plural sense amplifiers detect the data stored in the memorycells. Plural write drivers write data to the memory cells. A comparisonbuffer temporarily stores the write data to be written in the memorycells by the write driver. During a series of write sequences, thecomparison buffer stores the read data from memory cells selected as thewrite object (the storage destination) and the write data to be writtenin the selected memory cells. After the series of write sequences, whenthe pre-charge command for resetting the voltage of the bit lines isreceived, the write execution command is executed so that the comparisonbuffer executes a write to the selected memory cells of the write datastored in the comparison buffer.

Embodiment 1

FIG. 1 is a block diagram illustrating a magnetic random access memory(hereinafter to be referred to as MRAM) memory cell array and itsperipheral circuit according to Embodiment 1. In addition to the MRAM,the present embodiment may also be used in the memories (such as PCRAM,ReRAM, etc.) using resistance change type elements.

The MRAM in this embodiment has the following parts: a cell array unitCAU containing plural memory cell arrays MCA, plural main word linesMWL, plural local word lines LWL, plural read global data buses RGDB,plural write global data buses WGDB, sense amplifier S/A, read bufferRB, write driver W/D, write buffer WB, row controller RC, main rowdecoder MRD, column decoder CD, input/output gate circuit IOG, andread/write data line RWD. There is no specific restriction on thenumbers of the various structural elements shown in FIG. 1. Thecomponents shown in FIG. 1 may be arranged in various ways. In addition,while source lines are included in the actual device, they are not shownhere.

Each memory cell array MCA contains plural memory cells MC arranged in amatrix-shaped two-dimensional configuration. The memory cells MC arearranged at cross points between the bit lines BL and local word linesLWL shown in FIG. 3. The bit lines BL extend in the column direction,and the local word lines LWL extend in the row direction orthogonal tothe column direction.

The main word lines MWL are connected with the local row decoder LRD,and the local row decoder LRD is connected with the memory cells MC vialocal word lines LWL. In the respective cell array units CAU in thememory cell macros MCM, there is a one-to-one corresponding relationshipbetween the main word lines MWL and the local word lines LWL.Consequently, according to the present embodiment, there is no need todistinguish the main word lines MWL and the local word lines LWL fromeach other. The phrase “word lines” refers to both types.

Plural memory cell arrays MCA form a cell array unit CAU. As shown inFIG. 1, four memory cell arrays MCA form a cell array unit CAU. However,there is no specific restriction on the number of memory cell arrays MCAcontained in each cell array unit CAU.

The plural cell array units CAU that share the main word lines MWL forma memory cell macro MCM. The memory cell macro MCM is a unit that can beactivated under one read command to simultaneously read the data orsimultaneously write the data under one write command. Plural memorycell macros MCM that share the read global data bus RGDB and writeglobal data bus WGDB form a macro block MB. There is no specificrestriction on the number of the cell array units CAU contained in eachmemory cell macro MCM.

The sense amplifier S/A is arranged corresponding to plural bit linesBL. Sense amplifier S/A detects the data transmitted via specific bitlines among the plural bit lines BL. The write driver W/D is arrangedcorresponding to plural bit lines BL. The write driver W/D carries outwrite of data to the memory cells MC via specific bit lines among theplural bit lines BL.

Each cell array unit CAU has one or more sense amplifiers S/A and one ormore write drivers W/D. Plural sense amplifiers S/A in a memory cellmacro MCM are connected with different read global data buses RGDB.Plural write drivers W/D in a memory cell macro MCM are connected withdifferent write global data buses WGDB. That is, the read global databuses RGDB and the write global data buses WGDB are arranged with aone-to-one corresponding relationship with the sense amplifiers S/A andwrite drivers W/D, respectively. Consequently, the read global databuses RGDB are arranged corresponding to bit lines and sense amplifiersS/A and write global data buses WGDB are arranged corresponding to thebit lines BL and write drivers W/D, respectively.

The read global data buses RGDB and the write global data buses WGDBextend in the column direction. The main word lines MWL extend in therow direction orthogonal to the column direction.

The read global data buses RGDB each are connected to the read buffer RBvia column decoder CD. The write global data buses WGDB each areconnected to the write buffer WB via column decoder CD. Here, the columndecoder CD has the function of selecting the bit line BL according tothe column address. In this case, the column decoder CD selects anddrives one bit line BL with respect to one sense amplifier S/A.

The read buffer RB and write buffer WB are connected to the read/writedata lines RWD via the input/output gate circuit IOG. The read buffer RBamplifies the read data obtained from the corresponding read global databus RGDB and sends the obtained read data to the input/output gatecircuit IOG. The read buffer RB then sends the read data to outsideelements via the input/output gate circuit IOG. The write buffer WBamplifies the write data obtained from the read/write data line RWD, andsends the data to the memory cell macros MCM1 through MCM4.

The number of read/write data lines RWD is the same as the number ofpairs of read buffer RB and write buffer WB. That is, in this embodimentthere is one read/write data line RWD for each read buffer RB and writebuffer WB pair. Read/write data lines RWD can read the data outsimultaneously in parallel from one memory cell macro MCM. Theread/write data lines RWD also can fetch the write data from outside thememory chip for a memory cell macro in parallel with each other the sametime. For example, when the number of read buffer RB/write buffer WBpairs in one macro block MBA is 64, then 64 read/write data lines RWDare arranged corresponding to the pairs, respectively. As a result, thememory design would allow simultaneous reading or writing of 64-bitdata.

The main word lines MWL are connected to the row controller RC. The rowcontroller RC is connected to the main row decoder MRD. The main rowdecoder MRD decodes the row address. According to the row address, therow controller RC selects one main word line MWL from each of the pluralmemory cell macros MCM in the macro block MB. As the main word line MWLis selected, the one local word line LWL corresponding to the main wordline MWL is selected in each of the cell array units CAU. As a result,in the memory cell macro MCM, each sense amplifier S/A can detect thedata of the memory cell MC (hereinafter to be referred to as selectedmemory cell MC) corresponding to the cross point between the bit line BLselected by the column address and the main word line MWL (or the localword line LWL) selected by the row address. Also, in the memory cellmacro MCM, the respective write driver W/D can write the data into theselected memory cell MC.

According to the present embodiment, when the device is in a data writemode, the write data are temporarily stored in the comparison bufferCMPB (see FIG. 3) after being transmitted from input/output gate circuitIOG via the read/write data line RWD. The data of the write objectmemory cell MC from the selected page is also temporarily read in to thecomparison buffer CMPB. The write to the memory cell MC is not yetcarried out. Next, as the memory enters the pre-charge state, thecomparison buffer CMPB compares the write data with the correspondingread data from the memory cell, then, on the basis of the comparisonresult, the comparison buffer CMPB controls the write buffer WB suchthat only the write data different in logic from the read data arewritten to the memory cell macro MCM. Based on the comparison of readand write data the write driver W/D writes only the write data whichdoes not match the read data from the memory cell MC. When the logic ofthe read data is identical to the logic of the write data, thecomparison buffer CMPB controls the write buffer WB so that the writedata are not written in the memory cell macro MCM.

FIG. 2 is a diagram illustrating the components and operation of asingle memory cell MC. Here, the respective memory cell MC contain themagnetic tunnel junction element (MTJ) 10 and the cell transistor 20.The MTJ element 10 and the cell transistor 20 are connected in tandembetween the bit line BL and the source line SL. In the memory cell MC,the cell transistor 20 is arranged on the side neighboring the bit lineBL, and the MTJ element 10 is arranged on the side neighboring thesource line. The gate of the cell transistor 20 is connected to the wordline WL (main word line MWL or local word line LWL).

The MTJ element that exploits the TMR (tunneling magnetoresistive)effect has a laminated structure including two ferromagnetic layers anda nonmagnetic layer (insulating film) sandwiched between them, and itstores the digital data corresponding to change in the magneticresistance due to the spin polarization tunnel effect. The MTJ elementacquires a low resistance state or a high resistance state correspondingto the configuration of magnetization of two ferromagnetic layers. Forexample, the low resistance state is defined as 0, while the highresistance state is defined as 1, so that the MTJ element can record1-bit data. Of course, one may also use a scheme in which the lowresistance state is defined as 1 while the high resistance state isdefined as 0.

The MTJ element may be formed, for example, by sequentially laminatingan anchoring layer, a tunnel barrier layer, and a recording layer. Here,the anchoring layer F and the recording layer P are made offerromagnetic material, while the tunnel barrier layer is made of aninsulating film. The anchoring layer F is a layer that anchors theorientation of magnetization. The recording layer P can change itsorientation of magnetization, so that data can be stored correspondingto the orientation of the magnetization.

In the write mode, as a current flows in the direction indicated byarrow A1, the orientation of the recording layer P becomes theanti-parallel state with respect to the magnetization orientation of theanchoring layer F, and the state becomes the high resistance state (data1). On the other hand, when the current flows in the direction indicatedby arrow A2 in the write mode, the orientation of magnetization of theanchoring layer F and that of the recording layer P are parallel witheach other, and the state becomes the low resistance state (data 0). Inthis way, the TMJ element can be written with different data dependingon the current direction.

FIG. 3 is a diagram illustrating the connection relationship between theread global data bus RGDB as well as the write global data bus WGDB andthe memory cell macros MCM1 through MCM4. As shown in FIG. 3, as anexample, two memory cell arrays MCA are shown in each of the memory cellmacros MCM1 through MCM4. FIG. 3 shows only one sense amplifierS/A/write driver W/D pair and one read global data bus RGDB/write globaldata bus WGDB pair. However, in the practical structure, a plurality ofthese pairs is used.

The read global data bus RGDB is connected to the read buffer RB, andthe write global data bus WGDB is connected to the write buffer WB. Theread buffer RB and the write buffer WB are connected to the read/writedata line RWD via comparison buffer CMPB. The comparison buffer CMPB isassembled in the input/output gate circuit IOG.

The local row decoder LRD is arranged between memory cell arrays MCA ineach of the memory cell macros MCM1 through MCM4. The local row decoderLRD works as a buffer for driving the local word line LWL. Consequently,row controller RC drives word line WL via main word line MWL and localrow decoder LRD. In FIG. 3, the main word line MWL is not shown.

The memory cell macros MCM in the same macro block MB share a readglobal data bus RGDB and a write global data bus WGDB. But, the senseamplifiers S/A in the same memory cell macro MCM are connected todifferent read global data buses RGDB via plural read latch parts RLCH.The read latch parts RLCH are arranged corresponding to the senseamplifiers S/A, and each read latch part RLCH is connected between thesense amplifier S/A and a read global data bus RGDB. The read latch partRLCH latches the data detected by the sense amplifier S/A. The readlatch part RLCH contains a gated inverter In1 that outputs the latcheddata at the time determined by the output enable signal SOE_Ci (where irepresents an integer).

The write drivers W/D in the memory cell macro MCM are connected todifferent write global data buses WGDB via write latch parts WLCH. Thewrite latch parts WLCH are arranged corresponding to the write driversW/D, and each write latch part WLCH is connected between a correspondingwrite driver W/D and a write global data bus WGDB. The write latch partWLCH contains the gated inverter In2 that receives the write data fromthe write global data bus WGDB at the time determined by the inputenable signal WIE_Ci. As a result, the write latch part WLCH latches thedata to be sent to the write driver W/D.

The sense amplifier S/A and the write driver W/D are connected to thebit line BL selected by the column selection line CSL. As shown in FIG.3, while one memory cell array MCA is connected to the sense amplifierS/A, the other memory cell array MCA is connected to the write driverW/D. However, the memory cell array MCA can be connected to both thesense amplifier S/A and the write driver W/D via the column selectionline CSL. The voltage of the column selection line CSL is controlled bythe column decoder CD.

The comparison buffer CMPB is a circuit that temporarily stores thewrite data and the data stored in the selected memory cell MC where thedata are to be written in the data write operation, and it compares thelogic states of these data.

In the data read mode, one main word line MWL is selected in each memorycell macro MCM, and the data are simultaneously detected by the senseamplifiers S/A via read global data buses RGDB from the memory cells MCconnected to the selected main word line MWL. The data detected by thesense amplifiers S/A are temporarily stored in the corresponding readlatch parts RLCH. The output enable signals SOE_C1 through SOE_C4 arethen sequentially activated consecutively at different times such thatthe data are continuously output from the read latch parts RLCH of eachmemory cell macro MCM to the read global data buses RGDB. The read dataare then temporarily stored in the comparison buffer CMPB via the readglobal data bus RGDB. In this case, read latch parts RLCH in one memorycell macro MCM may simultaneously send the data to the correspondingread global data bus RGDB connected to them. As a result, it is possibleto transmit the data in parallel using all of the read global data busesRGDB without any waste in the macro block MB. On the other hand, theread latch parts RLCH in the different memory cell macros MCM of a macroblock MB transmit the data to the read global data buses RGDB atdifferent times. Thus, it is possible to continuously transmit pluraldata without collisions in the read global data buses RGDB.

In the data write mode, the comparison buffer CMPB temporarily storesthe write data received via the read/write data lines RWD. The inputenable signals WIE_C1 through WIE_C4 are then sequentially activatedconsecutively, and the data are continuously fetched into the writelatch parts WLCH of the respective memory cell macros MCM via the writeglobal data buses WGDB and the write buffers WB. In this case, the writelatch parts WLCH in one memory cell macro MCM may fetch the datasimultaneously from comparison buffers CMPB connected to them,respectively. As a result, data can be transmitted in parallel by usingall of the write global data buses WGDB in the macro block MB withoutwaste. On the other hand, the write latch parts WLCH of the differentmemory cell macros MCM in one macro block MB receive the data atdifferent times from one comparison buffer CMPB. Thus, it is possible tocontinuously transmit the plural data to the write latch parts WLCHwithout collision in the write global data buses WGDB.

FIG. 4 is a block diagram illustrating the internal components of acomparison buffer CMPB. The comparison buffer CMPB has a multiplexerMUX, D flip-flop circuits DFF1, DFF2, logic circuit LC, and gate circuitG1.

The multiplexer MUX is connected to the read buffer RB and write bufferWB, and it receives the read data RD1 through RD4 and the write dataRWD1 through RWD4. The read data RD1 through RD4 and write data RWD1through RWD4 correspond to the memory cell macros MCM1 through MCM4,respectively.

The multiplexer MUX transmits any of the read data RD1 through RD4 andwrite data RWD1 through RWD4 selectively to the D flip-flop circuitDFF1. For example, when the read commands CBR_LTC1 through CBR_LTC4 areactivated, the multiplexer MUX selects the read data RD1 through RD4;when the write commands CBW_LTC1 through CBW_LTC4 are activated, itselects write data RWD1 through RWD4.

The gate circuit G1 is a NOR gate. The read commands CBR_LTC1 throughCBR_LTC4 and write commands CBW_LTC1 through CBW_LTC4 are input to itand, the latch command LTC1 to the D flip-flop circuit DFF1 is activatedwhen any of these commands are active.

At the time of activation of latch commands LTC1_1 through LTC1_4, the Dflip-flop circuit DFF1 as the first latch part latches the read data RD1through RD4 or write data RWD1 through RWD4 from the multiplexer MUX.

At the time of activation of latch commands LTC2_1 through LTC2_4 (by,for example, activation of the read commands CBR_LTC1 through CBR_LTC4),the D flip-flop circuit DFF2 as the second latch part latches the readdata RD1 through RD4.

The D flip-flop circuits DFF1, DFF2 are set so that the read dataobtained via the read global data buses RGDB and read buffer RB can beheld as one page portion (for example, 128 bits). The D flip-flopcircuit DFF1 is set so that it can hold one page portion (for example,128 bits) of the write data obtained via the read/write data line RWD.

The logic circuit LC as the logic part receives the pre-charge commandPRECH and read data RD1 through RD4 or write data RWD1 through RWD4latched in the D flip-flop circuits DFF1, DFF2. On the basis of thepre-charge command PRECH and the read data RD1 through RD4 and writedata RWD1 through RWD4, the write execution command CBW is activated bythe logic circuit LC. The logic circuit LC outputs the write executioncommand CBW to the write buffer WB. For example, at the time ofactivation of the pre-charge command PRECH, the logic circuit LCcompares the logic of the read data RD1 through RD4 from the D flip-flopcircuit DFF2 with the logic of the read data RD1 through RD4 or thewrite data RWD1 through RWD4 from the D flip-flop circuit DFF1. When thelogic states of these data are different, the logic circuit LC activatesthe write execution command CBW. When these data have the same logic,the logic circuit LC maintains the inactive state for the writeexecution command CBW (i.e., the write execution command CBW is notactivated).

When the write execution command CBW is activated, the write buffer WEsends the write data of the corresponding address among the write datastored in the D flip-flop circuit DFF1 to the write driver W/D. When thewrite execution command CBW is in the inactive state, the write bufferWE does not send the write data of the corresponding address among thewrite data stored in the D flip-flop circuit DFF1 to the write driverW/D. In addition, the pre-charge commands PRECH1 through PRECH4 have thebank address (the address of the memory cell macro MCM). Consequently,when the write buffer WB receives the pre-charge commands PRECH1 throughPRECH4, it may transfer the write data to any of the memory cell macrosMCM1 through MCM4 according to the bank address.

The logic circuit LC is shared by the plural write data RWD1 throughRWD4 and plural read data RD1 through RD4. In this case, the logiccircuit LC may execute a comparison between the write data RWD1 throughRWD4 and the read data RD1 through RD4 at different times.

(Data Write Operation)

FIG. 5 is a time diagram illustrating the data write operation of thememory according to Embodiment 1. Here, for example, it is assumed forexplanation purposes that each macro block MB contains the four memorycell macros MCM1 through MCM4. Consequently, the write operation (writesequence) to the respective memory cell macros MCM1 through MCM4 isstarted by the four write commands W1 through W4.

In the data write operation according to the present embodiment, thesense amplifier S/A reads the data from the memory cell MC selected asthe write object (the selected memory cell MC), and the read data fromthe selected memory cell MC are stored in the comparison buffer CMPB.Also, the comparison buffer CMPB receives the write data to be writtenin the selected memory cell MC from the read/write data line RWD andstores the write data. That is, before the data are actually written,the data are read from the selected memory cell MC. Consequently, on thebasis of the write commands W1 through W4, the read commands CBR_LTC1through CBR_LTC4 are also activated.

In the following, the data write operation will be explained in moredetail.

According to clock CK_t, the addresses CA (column address, row address,etc.) and the various types of commands Cmd (active command A, writecommands W1 through W4, etc.) are sent to the memory. According to therow address, one main word line MWL is selected in each memory cellmacro MCM, and the local word line LWL in each cell array unit CAUconnected to the selected main word line MWL is also selected. Inaddition, according to the column address, the bit line BL connected tothe respective sense amplifier S/A in the memory cell macro MCM isselected. The multiple sense amplifiers S/A in the memory cell macro MCMcan simultaneously read the data from the selected memory cells MCconnected to the selected bit lines BL and the selected local word linesLWL.

At t0, the memory receives the active command A, and the row address isselected. Next, as the memory receives the write commands W1 through W4,the column address is selected.

As the word enable signal bMWL is activated on the low level, accordingto the row address, it is possible to drive the word lines LWL_C1through LWL_C4. When the column selection line CSL is activated on thehigh level, as explained with reference to FIG. 3, the bit line BLselected according to the column address is connected to the senseamplifier S/A. As a result, the sense amplifiers S/A of the respectivememory cell macros MCM1 through MCM4 can detect the data of the selectedmemory cells MC. The data detected by the sense amplifiers S/A arelatched in the read latch part RLCH.

Accompanying the reception of the write commands W1 through W4, at thetime of t1 through t4, the output enable signals SOE_C1 through SOE_C4are continuously activated. As a result, the read data latched in theread latch parts RLCH of the memory cell macros MCM1 through MCM4 aresent continuously via the read global data buses RGDB to the comparisonbuffer CMPB. Next, accompanying the reception of the write commands W1through W4, at the time of t1 through t5, the read commands CBR_LTC1through CBR_LTC4 are continuously activated.

When the read command CBR_LTC1 is activated at t2, the data read fromthe memory cell macro MCM1 are held in both the D flip-flop circuitsDFF1, DFF2 of the comparison buffer CMPB shown in FIG. 4. Similarly,when the read command CBR_LTC2 is activated at t3, the data read fromthe memory cell macro MCM2 are held in both the D flip-flop circuitsDFF1, DFF2 of the comparison buffer CMPB. When the read command CBR_LTC3is activated at t4, the data read from the memory cell macro MCM3 areheld in both the D flip-flop circuits DFF1, DFF2 of the comparisonbuffer CMPB. When the read command CBR_LTC4 is activated at t5, the dataread from the memory cell macro MCM4 are held in both the D flip-flopcircuits DFF1, DFF2 of the comparison buffer CMPB. As a result, therespective read data of the memory cell macros MCM1 through MCM4 arestored in the D flip-flop circuits DFF1, DFF2 of the comparison bufferCMPB.

In addition, because the address indicated by the read command CBR_LTC2is different from the address indicated by the read command CBR_LTC1,the D flip-flop circuits DFF1, DFF2 hold the data read from the memorycell macro MCM2 aside (separate) from the read data from the memory cellmacro MCM1 and the write data to the memory cell macro MCM1. Also,because the address indicated by the read command CBR_LTC3 is differentfrom the address indicated by the read command CBR_LTC1 and CBR_LTC2,the D flip-flop circuits DFF1, DFF2 hold the read data from the memorycell macro MCM3 aside from the read data from memory cell macros MCM1,MCM2 and the write data to the memory cell macros MCM1, MCM2. Inaddition, because the address indicated by the read command CBR_LTC4 isdifferent from the address indicated by the read commands CBR_LTC1through CBR_LTC3, the D flip-flop circuits DFF1, DFF2 hold the read datafrom the memory cell macro MCM4 aside from the read data from the memorycell macros MCM1 through MCM3 and the write data to the memory cellmacros MCM1 through MCM3.

At the time of t1 through t5, the write data are sent to the comparisonbuffer CMPB via the data line DQ. At the time of t3 through t9,according to the write commands CBW_LTC1 through CBW_LTC4, thecomparison buffer CMPB stores the write data RWD1 through RWD4.

(Operation According to Write Command CBW_LTC1)

At time t3 after activation of the read command CBR_LTC1, the writecommand CBW_LTC1 is activated. Here, the write command CBW_LTC1corresponds to the read command CBR_LTC1, and it has the address of theselected memory cell MC of the memory cell macro MCM1. That is, thewrite data sent to the comparison buffer CMPB due to activation of thewrite command CBW_LTC1 are data having the same address as the read datasent to the comparison buffer CMPB due to activation of the read commandCBR_LTC1.

As the write command CBW_LTC1 is activated, the D flip-flop circuit DFF1of the comparison buffer CMPB shown in FIG. 4 holds the write data. Inthis case, the read data stored in the D flip-flop circuit DFF1 arerefreshed (overwritten) by the write data. This is because the writecommand CBW_LTC1 and the read command CBR_LTC1 show the selected memorycells MC with the same address.

As a result, the read data from the selected memory cell MC of thememory cell macro MCM1 are held in the D flip-flop circuit DFF2. Thedata to be written in the selected memory cell MC of the memory cellmacro MCM1 are held in the D flip-flop circuit DFF1.

Afterwards, at the time of t4 through t6, the write command CBW_LTC1 isactivated. This means that the memory continuously receives the writedata of the same address. In the series of write sequences, when pluralwrite data of the same address are received, the finally received writedata are the effective data. Consequently, the data to be written in theselected memory cell MC of the memory cell macro MCM1 are refreshed eachtime that activation of the write command CBW_LTC1 is carried out at thetime of t1 through t4. The D flip-flop circuit DFF1 then effectivelyholds the write data RWD1 finally received at time t6. For example,suppose during the time of t4 through t6, the write command CBW_LTC1 isactivated four times with the incoming write data being 1, 1, 1, 0,respectively. The finally received piece of data “0” is taken as thewrite data RWD1 that will be written to the selected memory cell MC.

(Operation According to Write Command CBW_LTC2)

At t4 after activation of the read command CBR_LTC2, the write commandCBW_LTC2 is activated. The write command CBW_LTC2 corresponds to theread command CBR_LTC2, and it has the address of the selected memorycell MC of the memory cell macro MCM2.

As the write command CBW_LTC2 is activated, as shown in FIG. 4, the Dflip-flop circuit DFF1 of the comparison buffer CMPB holds the writedata. In this case, due to activation of the read command CBR_LTC2, theread data stored in the D flip-flop circuit DFF1 are refreshed by thewrite data. This is because the write command CBW_LTC2 and the readcommand CBR_LTC2 show the selected memory cells MC of the same address.

As a result, the read data from the selected memory cell MC of thememory cell macro MCM2 are held in the D flip-flop circuit DFF2, and thedata to be written in the selected memory cell MC of the memory cellmacro MCM2 are held in the D flip-flop circuit DFF1.

In this write sequences, the write command CBW_LTC2 is activated onlyonce. Consequently, the D flip-flop circuit DFF1 effectively holds thewrite data RWD2 received at time t4.

Because the address shown in the write command CBW_LTC2 is differentfrom the address shown in the write command CBW_LTC1, the D flip-flopcircuit DFF1 holds the write data RWD2 aside from the write data RWD1.For the read data RD2, the D flip-flop circuit DFF2 holds the read dataRD2 aside from the read data RD1.

(Operation According to Write Command CBW_LTC3)

At t5 after activation of the read command CBR_LTC3, the write commandCBW_LTC3 is activated. The write command CBW_LTC3 corresponds to theread command CBR_LTC3, and it has the address of the selected memorycell MC of the memory cell macro MCM3.

When the write command CBW_LTC3 is activated, as shown in FIG. 4, the Dflip-flop circuit DFF1 of the comparison buffer CMPB holds the writedata. In this case, the read data stored in the D flip-flop circuit DFF1due to activation of the read command CBR_LTC3 are refreshed by thewrite data. This is because the write command CBW_LTC3 and the readcommand CBR_LTC3 show the selected memory cells MC of the same address.

As a result, the read data from the selected memory cell MC of thememory cell macro MCM3 are held in the D flip-flop circuit DFF2, and thedata to be written in the selected memory cell MC of the memory cellmacro MCM3 are held in the D flip-flop circuit DFF1.

In this write sequences, the write command CBW_LTC3 is activated twice.The D flip-flop circuit DFF1 effectively holds the last write data RWD3fetched at t6.

Because the address indicated by the write command CBW_LTC3 is differentfrom the address indicated by the write commands CBW_LTC1 and CBW_LTC2,the D flip-flop circuit DFF1 holds the write data RWD3 aside from thewrite data RWD1 and RWD2. For the read data RD3, also, the D flip-flopcircuit DFF2 holds the read data RD3 aside from the read data RD1 andRD2.

(Operation According to the Write Command CBW_LTC4)

At t6 after activation of the read command CBR_LTC4, the write commandCBW_LTC4 is activated. The write command CBW_LTC4 corresponds to theread command CBR_LTC4, and it has the address of the selected memorycell MC of the memory cell macro MCM4.

As the write command CBW_LTC4 is activated, as shown in FIG. 4, the Dflip-flop circuit DFF1 of the comparison buffer CMPB holds the writedata. In this case, the read data stored in the D flip-flop circuit DFF1due to activation of the read command CBR_LTC4 are refreshed by thewrite data. This is because the write command CBW_LTC4 and read commandCBR_LTC4 indicate the selected memory cells MC of the same address.

As a result, the read data from the selected memory cell MC of thememory cell macro MCM4 are held in the D flip-flop circuit DFF2, and thedata to be written in the selected memory cell MC of the memory cellmacro MCM4 are held in the D flip-flop circuit DFF1.

In this write sequences, the write command CBW_LTC4 is activated thrice.The D flip-flop circuit DFF1 effectively holds the last write data RWD4received at t8.

Because the address indicated by the write command CBW_LTC4 is differentfrom the address indicated by the write commands CBW_LTC1 throughCBW_LTC3, the D flip-flop circuit DFF1 holds the write data RWD4 asidefrom the write data RWD1 through RWD3. For the read data RD4, also, theD flip-flop circuit DFF2 holds the read data RD4 aside from the readdata RD1 through RD3.

In this way, according to the present embodiment, the comparison bufferCMPB latches the write data RWD1 through RWD4 and read data RD1 throughRD4 corresponding to the addresses of the plural selected memory cellsMC in a series of respective write sequences.

Afterwards, after receiving a series of write commands W1 through W4,the write sequence comes to an end, and the pre-charge commands PRECH1through PRECH4 are activated. The number of pre-charge commands PRECH1through PRECH4 generated is equal to the number (bank number) of thememory cell macros MCM that execute the interleaved operation. Afterreceiving the activation of the pre-charge commands PRECH1 throughPRECH4, the logic circuit LC of the comparison buffer CMPB compares thelogic of the read data RD1 through RD4 with that of the write data RWD1through RWD4 for each of their addresses. In this case, the logiccircuit LC detects the difference/identity in the logic of the outputdata of the D flip-flop circuits FFD1 and FFD2 for each address.

Next, when the read data RD1 through RD4 and the write data RWD1 throughRWD4 have different logic states, the logic circuit LC activates thewrite execution commands CBW_A1 through CBW_A4. For example, when theread data RD1 and write data RWD1 have different logic states, the logiccircuit LC activates the write execution command CBW_A1.

When the read data RD1 through RD4 and the write data RWD1 through RWD4have the same logic, the logic circuit LC does not activate the writeexecution commands CBW_A1 through CBW_A4; instead, it keeps them in theinactive state. For example, when the read data RD2 and write data RWD2have the same logic state, the logic circuit LC does not activate thewrite execution command CBW_A2; instead, it keeps the command in theinactive state.

In the example shown in FIG. 5, the read data RD1 and the write dataRWD1 have different logic states, as do the read data RD4 and write dataRWD4. On the other hand, the write data RWD2 and RWD3 has the same logicread data RD2 and RD3, respectively. Consequently, the logic circuit LCactivates the write execution commands CBW_A1 and CBW_A4 (t10, t13),while it keeps the write execution commands CBW_A2 and CBW_A3 in theinactive state.

Next, corresponding to the activation of the write execution commandsCBW_A1, CBW_A4, the write buffer WB sends the write data RWD1, RWD4 viathe write global data bus WGDB to the write drivers W/D of the memorycell macros MCM1, MCM4. Here, because the write data RWD1, RWD4 arestored in the D flip-flop circuit DFF1, respectively, they are sent fromthe D flip-flop circuit DFF1.

For example, at t11, the input enable signal WIE_C1 is activated, andthe write latch part WLCH of the memory cell macro MCM1 receives thewrite data RWD1. At t14, the input enable signal WIE_C4 is activated,and the write latch part WLCH of the memory cell macro MCM4 receives thewrite data RWD4. On the other hand, the input enable signals WIE_C2,WIE_C3 for the memory cell macros MCM2, MCM3, which will not havedifferent data written to them, are not activated.

Next, as the respective write drivers W/D of the memory cell macrosMCM1, MCM4 receive the write data RWD1, RWD4, within the pre-chargeperiod, the write data RWD1, RWD4 are written in the selected memorycells MC of the memory cell macros MCM1, MCM4.

As explained above, according to the present embodiment, in the datawrite operation, the data of the selected memory cell MC as the writeobject are read, and the comparison buffer CMPB compares the logic ofthe read data RD1 through RD4 with the logic of the write data RWD1through RWD4. If the logic of the read data is different from the logicof the write data, the write driver W/D writes the write data to thecorresponding selected memory cell. On the other hand, if the logic ofthe read data is identical to the logic of the write data, the writedriver W/D does not write the write data to the corresponding selectedmemory cell.

Consequently, the write driver W/D may execute the write operation tothe selected memory cell MC (that is, cell current may be made to flowto the selected memory cell MC) only in the memory cell macros MCM1,MCM4 that have the logic of the write data different from the logic ofthe data already stored in the selected memory cell MC. On the otherhand, for the memory cell macros MCM2, MCM3 with the logic of the writedata identical to the logic of the data stored in the selected memorycell MC, there is no need for the write driver W/D to carry out writeoperation to the selected memory cell MC (that is, there is no need tohave a cell current flow to the selected memory cell MC). As a result,it is possible to suppress the wasteful power consumption in the datawrite operation.

In addition, according to the present embodiment, the write data RWD1through RWD4 fetched by a series of write commands W1 through W4 aretemporarily stored in the comparison buffer CMPB. After the reception ofa series of write commands W1 through W4, the pre-charge commands PRECH1through PRECH4 are activated, so that the comparison buffer CMPBactivates the write execution commands CBW_A1 through CBW_A4. As aresult, the write driver W/D executes the actual write operation to theselected memory cell MC during the pre-charge period. Consequently, thewrite time from the viewpoint of the user is only the time of data writeto the write buffer WB, and the actual write time to the selected memorycell MC is not sensed by the user. As a result, according to the presentembodiment, the MRAM has an extremely high write operation speed, and aninterleaved write operation can be easily carried out.

In addition, because the four pre-charge commands PRECH1 through PRECH4have the addresses (bank addresses) of the memory cell macros MCM1through MCM4 respectively, it is possible to have the write operation tothe respective memory cell macros MCM1 through MCM4 dispersed in timeduring the pre-charge period. As a result, it is possible to preventsimultaneous write operation to plural memory cell macros MCM, and it ispossible to suppress instant surge of the current consumption. That is,according to the present embodiment, the MRAM can have an even writecurrent.

In addition, in a series of write sequences when write data of the sameaddress are continuously input, the comparison buffer CMPB holds onlythe last received write data RWD1 through RWD4. During the pre-chargeperiod, the write driver W/D writes the last received write data RWD1through RWD4 to the selected memory cells MC. Consequently, even when amemory cell MC of the same memory cell macro MCM is repeatedly accessedover a short time (that is, a time shorter than the time needed forwrite of the data to the MTJ element), there will still be no defectivewrite and the necessary time for writing the data to the MTJ element canbe sufficiently obtained.

In addition, there is no specific restriction on the capacity of thewrite data and read data stored in the comparison buffer CMPB. In aseries of write sequences, the comparison buffer CMPB may store two ormore pages of data in each of the read buffer RB and the write bufferWB. Each page is a data read unit or a data write unit.

(Data Read Operation)

In the data read operation in which the data are read to the outside,the data are temporarily stored in the comparison buffer CMPB, and theyare then output to the outside via the read/write data line RWD. Thedata read operation through the step involving storage of the read datain the comparison buffer CMPB can be easily understood with reference toFIG. 5 and the accompanying explanation above. Consequently, theoperation from detection of the read data to storage of the data in thecomparison buffer CMPB will not be explained repeatedly. However,instead of the write commands W1 through W4 supplied previously, thememory receives the read commands R1 through R4, and the read operationis executed on the basis of the read commands R1 through R4.

As shown in FIG. 4, when the D flip-flop circuits DFF1, DFF2 of thecomparison buffer CMPB receive the read commands CBR_LTC1 throughCBR_LTC4, both of them hold the read data RD1 through RD4. Next, as thewrite command is not input, the data of the same address and latched inthe D flip-flop circuits DFF1, DFF2 have the same logic. Consequently,in the data read operation, the logic circuit LC does not set the writeexecution commands CBW_A1 through CBW_A4 to the active state, and thewrite buffer WB does not operate.

The comparison buffer CMPB may output the read data stored in the Dflip-flop circuit DFF1 via the read/write data line RWD withoutalteration.

Also, as shown in FIG. 3, the read latch parts RLCH of the respectivememory cell macros MCM1 through MCM4 send the data sequentially to theread global data bus RGDB on the basis of the output enable signalsSOE_C1 through SOE_C4. Consequently, it is possible to carry out a burstread operation.

Embodiment 2

FIG. 6 is a block diagram illustrating the components of an MRAM deviceaccording to Embodiment 2. According to Embodiment 2, the read globaldata bus RGDB and the write global data bus WGDB are shared, and theyare set as the global data bus RWGDB. The read latch part RLCH and writelatch part WLCH of the respective memory cell macros MCM1 through MCM4are both connected to the global data bus RWGDB, and they are thenconnected to the comparison buffer CMPB via the global data bus RWGDB.Consequently, while the comparison buffer CMPB in Embodiment 1 is of thedual port type, the comparison buffer CMPB in Embodiment 2 is of thesingle port type.

As shown in FIG. 5, in the data write operation, the time fortransferring the write data in the write global data bus WGDB (t11 tot14) is during the pre-charge period. Consequently, the time of transferof the write data in the write global data bus WGDB does not overlap thetime (t1 to t5) in which the transfer of the read data in the readglobal data bus RGDB occurs. Consequently, there is no problem even whenthe global data bus RWGDB is shared as in Embodiment 2. The read bufferRB and the write buffer WB can, therefore, be connected to the sharedglobal data bus RWGDB. The functions of the read buffer RB and the writebuffer WB are the same as in Embodiment 1. The remaining features ofEmbodiment 2 may be the same as the corresponding features in Embodiment1.

FIG. 7 is a time diagram illustrating the data write operation of thememory according to Embodiment 2. Here, the global data bus RWGDB isshared for read and write, and the read data and the write data aretransferred at different times. The remaining features of the operationaccording to Embodiment 2 may be the same as those of the correspondingfeatures of the operation according to Embodiment 1.

According to Embodiment 2, the same effects as those of Embodiment 1 canbe realized. In addition, according to Embodiment 2, the global data busRWGDB is shared for the read and write, so that the separate read bufferRB and write buffer WB are omitted. Consequently, the MRAM according toEmbodiment 2 is favorable for forming smaller memory chips.

Embodiment 3

FIG. 8 is a block diagram illustrating the components of the MRAMaccording to Embodiment 3. According to Embodiment 3, ECC (errorcorrecting code) decoder ECCDEC is arranged between the read buffer RBand the comparison buffer CMPB, and ECC encoder ECCENC is arrangedbetween the write buffer WB and the comparison buffer CMPB. The otherfeatures of Embodiment 3 may be the same as the corresponding featuresof Embodiment 1.

FIG. 9 is a block diagram illustrating the components of the comparisonbuffer CMPB according to Embodiment 3. The components of the comparisonbuffer CMPB itself is the same as the components of the comparisonbuffer CMPB in Embodiment 1. However, multiplexer MUX receives the readdata PRD1 through PRD4 corrected by the ECC decoder ECCDEC.Consequently, by means of activation of the read commands CBR_LTC1through CBR_LTC4, the D flip-flop circuit DFF1 latches the correctedread data PRD1 through PRD4.

The data write operation according to Embodiment 3 is otherwise the sameas the data write operation according to Embodiment 1. As explained withreference to FIG. 5, by means of activation of the read commandsCBR_LTC1 through CBR_LTC4, the D flip-flop circuit DFF1 latches thecorrected read data PRD1 through PRD4. However, after that, as the writecommands CBE_LTC1 through CBE_LTC4 are activated, the D flip-flopcircuit DFF1 is updated by the write data RWD1 through RWD4.

Consequently, the comparison buffer CMPB compares the read data RD1through RD4 actually stored in the selected memory cell MC with thewrite data RWD1 through RWD4. On the other hand, in the data readoperation in which the data are read to the outside, the D flip-flopcircuit DFF1 stores the corrected read data PRD1 through PRD4, and the Dflip-flop circuit DFF2 stores the read data RD1 through RD4.Consequently, when the corrected read data PRD1 through PRD4 and theread data RD1 through RD4 are different from each other, the logiccircuit LC activates the write execution commands CBW_A1 through CBW_A4.As a result, the write buffer WB has the corrected read data PRD1through PRD4 held in the D flip-flop circuit DFF1 written in the memorycell MC. That is, when the logic of the data stored in the memory cellsMC is incorrect, the comparison buffer CMPB can write the corrected readdata PRD1 through PRD4 to correct the memory cells MC.

In this way, Embodiment 3 may also be used on the MRAM having an ECCcircuit. The remaining features of operation of Embodiment 3 may be thesame as those of Embodiment 1. As a result, Embodiment 3 also canrealize the same effects as those of Embodiment 1.

Embodiment 4

FIG. 10 is a block diagram illustrating the components of the MRAMaccording to Embodiment 4. Embodiment 4 is a combination of Embodiment 2and Embodiment 3. That is, according to Embodiment 4, the read globaldata bus RGDB and the write global data bus WGDB are shared, and theyare set as the global data bus RWGDB. Also, an ECC decoder ECCDEC andECC encoder ECCEN are arranged between the comparison buffer CMPB andthe read buffer RB as well as the write buffer WB.

Just as in Embodiment 2, the global data bus RWGDB is shared for readand write. However, the read data and the write data are transferred atdifferent times. Consequently, even when the global data bus RWGDB shownin FIG. 10 is shared, there is still no problem. Also, because the MRAMhas the ECC circuit ECCDEC and ECCENC, the comparison buffer CMPB worksin the same way as the comparison buffer CMPB in Embodiment 3.

As a result, Embodiment 4 has both the effects of Embodiment 2 andEmbodiment 3.

Embodiment 5

FIG. 11 is a block diagram illustrating the components of the MRAMaccording to Embodiment 5. FIG. 12 is a block diagram illustrating thecomponents of the comparison buffer CMPB according to Embodiment 5. Asshown in FIG. 11, in the comparison buffer CMPB, the logic circuits LC1through LC4 are arranged in the memory cell macros MCM1 through MCM4,respectively. The logic circuits LC1 through LC4 have a similarcomponents and function as that of the logic circuit LC in Embodiment 1.The logic circuits LC1 through LC4 are connected to the read latch partRLCH and receive the read data RD1 through RD4 from the read latch partRLCH directly, not through the read global data bus RGDB. The logiccircuits LC1 through LC4 are connected to the write latch part WLCH andtransfer the write data RWD1 through RWD4 directly to the write latchpart WLCH, not through the write global data bus WGDB.

The multiplexer MUX, D flip-flop circuit DFF1, and gate circuit G1 areset between the read buffer RB as well as write buffer WE and theread/write data line RWD just as in the other embodiments.

Because the logic circuits LC1 through LC4 directly receive the readdata RD1 through RD4, as shown in FIG. 12, the D flip-flop circuit DFF2of the comparison buffer CMPB can be omitted. The components of the Dflip-flop circuit DFF1, multiplexer MUX and gate circuit G1 may be thesame as that shown in FIG. 4. Consequently, the multiplexer MUX receivesthe read data RD1 through RD4 (or the corrected read data PRD1 throughPRD4) via the read global data bus RGDB.

In this way, the comparison buffer CMPB, according to Embodiment 5,directly receives the read data RD1 through RD4 from the read latch partRLCH, so that there is no need to have a D flip-flop circuit DFF2.However, it is necessary to arrange the logic circuits LC1 through LC4individually so that the read data RD1 through RD4 can be receivedsimultaneously.

(Data Write Operation)

In the data write operation, as the read data RD1 through RD4 arelatched in the read latch part RLCH, shown in FIG. 11, the read data RD1through RD4 are directly sent to the logic circuits LC1 through LC4.Also, the read data RD1 through RD4 are stored in the D flip-flopcircuit DFF1 via the read global data bus RGDB. The operation forstorage of the read data RD1 through RD4 in the D flip-flop circuit DFF1in the comparison buffer CMPB is the same as the corresponding operationin Embodiment 1. Also, the operation of holding of the write data RWD1through RWD4 in the D flip-flop circuit DFF1 is the same as thecorresponding operation in Embodiment 1. Consequently, after the readdata RD1 through RD4 are stored in the D flip-flop circuit DFF1, theyare refreshed by means of write data RWD1 through RWD4. Thus, the Dflip-flop circuit DFF1 stores the write data RWD1 through RWD4.

After the end of a series of write sequences, the pre-charge commandsPRECH1 through PRECH4 are sequentially activated. As a result, the logiccircuits LC1 through LC4 compare the write data RWD1 through RWD4 withthe read data RD1 through RD4. When the logic of the write data RWD1through RWD4 is different from the logic of read data RD1 through RD4,the logic circuits LC1 through LC4 activate the write execution commandsCBW_A1 through CBW_A4.

The write data RWD1 through RWD4 are sent to the logic circuits LC1through LC4 and the write latch parts WLCH of the memory cell macrosMCM1 through MCM4 respectively. The write latch parts WLCH of the memorycell macros MCM1 through MCM4 latch the write data RWD1 through RWD4respectively.

The write execution commands CBW_A1 through CBW_A4 are directly fed fromthe logic circuits LC1 through LC4 to the write driver W/D.Consequently, as the write execution commands CBW_A1 through CBW_A4 areactivated, the write driver W/D starts the write operation for the writedata RWD1 through RWD4.

After the end of a series of write sequences, the memory enters thepre-charge state. According to Embodiment 5, the write data RWD1 throughRWD4 are sent to the write latch part WLCH either directly or via thelogic circuits LC1 through LC4. Consequently, the pre-charge commandsPRECH1 through PRECH4 that activate the write execution commands CBW_A1through CBW_A4 may be simultaneously activated. That is, the memory cellmacros MCM1 through MCM4 may be simultaneously set in the pre-chargestate.

According to Embodiment 5, the logic circuit should be arranged for eachof the memory cell macros MCM1 through MCM4. However, the D flip-flopcircuit DFF2 can be omitted. Also, it is possible to simultaneouslypre-charge the memory cell macros MCM1 through MCM4. Embodiment 5 alsocan realize the effects of Embodiment 1.

Although not shown in the figure, Embodiment 5 may be used in Embodiment2. That is, according to Embodiment 5, the read global data bus RGDB andthe write global data bus WGDB may be shared and set as the global databus RWGDB. In this case, Embodiment 5 can also realize the effects ofEmbodiment 2.

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, the novel embodiments described hereinmay be embodied in a variety of other forms; furthermore, variousomissions, substitutions and changes in the form of the embodimentsdescribed herein may be made without departing from the spirit of theinventions. The accompanying claims and their equivalents are intendedto cover such forms or modifications as would fall within the scope andspirit of the inventions.

What is claimed is:
 1. A semiconductor storage device comprising: amemory cell array containing a plurality of memory cells; a write driverfor writing data to the plurality of memory cells; and a comparisonbuffer configured to temporarily store both data read from the memorycells and data to be written to the memory cells, compare the data readfrom the memory cells to the data to be written to the memory cells togenerate a subset of the data to be written, and supply the subset ofthe data to be written to the write driver.
 2. The semiconductor storagedevice of claim 1, wherein the memory cell array has an MRAM structure.3. The semiconductor storage device of claim 1, wherein the comparisonbuffer includes error correction circuits for correcting data to bewritten.
 4. The semiconductor storage device of claim 1, wherein thecomparison buffer is of a single-port design.
 5. The semiconductorstorage device of claim 1, wherein the comparison buffer is located inan input/output gate circuit.
 6. The semiconductor storage device ofclaim 1, wherein the comparison buffer has at least one logic circuitlocated in a memory cell macro.
 7. A semiconductor storage devicecomprising: a plurality of bit lines; a plurality of word lines; amemory cell array containing a plurality of memory cells that areconnected with the bit lines and the word lines; a plurality of senseamplifiers which read data stored in the memory cells; a plurality ofwrite drivers that are configured to write data in the memory cells; anda comparison buffer that is configured to temporarily store write datato be written in the memory cells and data read from the memory cells,compare the write data with the read data to produce data to be actuallywritten, and issue a write execution command when a pre-charge commandfor resetting a voltage of the bit lines is received by the comparisonbuffer, as a result of which the data to be actually written is writtento the memory cells by the write drivers, wherein the comparison buffercomprises: a first latch part that holds the write data to be written; asecond latch part that holds the read data; and a logic part that worksas follows: when the pre-charge command is activated, the read data fromthe second latch part is compared with the write data from the firstlatch part, and if the read data is different from the write data, thewrite execution command is activated, and during a data read operation,the first and second latch parts both hold the read data, the logic partmaintains the write execution command in an inactive state, and dataread from the memory cells during a data read operation is held in thefirst latch part before being overwritten by the write data.
 8. Thesemiconductor storage device according to claim 7, wherein, if the readdata is different from the write data to be written, the comparisonbuffer activates the write execution command; on the other hand, if theread data is identical to the write data to be written, the comparisonbuffer does not activate the write execution command.
 9. Thesemiconductor storage device according to claim 7, further comprising: awrite buffer for sending the write data stored in the comparison bufferto the memory cells; wherein the comparison buffer outputs the writeexecution command to the write buffer; and when the read data and thewrite data to be written are different from each other, the write buffersends the write data to the memory cells; on the other hand, when theread data is identical to the write data to be written, the write bufferdoes not send the write data to the memory cells.
 10. The semiconductorstorage device according to claim 7, wherein the comparison buffercomprises: a first latch part that holds the write data to be written; asecond latch part that holds the read data; and a logic part that worksas follows: when the pre-charge command is activated, the read data fromthe second latch part is compared with the write data from the firstlatch part, and if the read data is different from the write data, thewrite execution command is activated.
 11. The semiconductor storagedevice according to claim 10, wherein the read data held in the firstlatch part are overwritten by the write data.
 12. The semiconductorstorage device according to claim 10, wherein during a data readoperation, the first and second latch parts both hold the read data, andthe logic part maintains the write execution command in an inactivestate.
 13. The semiconductor storage device according to claim 10 7,further comprising: an error correction part that corrects the an errorof the read data from the selected memory cells; wherein during a dataread operation, the first latch part holds the read data as corrected bythe error correction part;, and when the corrected read data held in thefirst latch part is different from the read data held in the secondlatch part, the logic part sets the write execution command in an activestate.
 14. The semiconductor storage device according claim 7, whereinthe read data and write data compared by the comparison buffer have thesame address.
 15. A method of writing data to a non-volatile storagedevice, comprising: selecting a memory address to be written withincoming data; reading data already stored at the memory address;storing the data read from the memory address in a comparison buffer;storing the incoming data in the comparison buffer, such that both dataread from the memory address and the incoming data are stored in thecomparison buffer; comparing, in the comparison buffer, the incomingdata and the data read from the memory address; and based on thecomparison in the comparison buffer, writing the incoming data to thememory address only when the incoming data differs from the data readfrom the memory address, wherein the comparison buffer comprises amultiplexer, a NOR gate, a first D flip-flop gate, a second D flip-flopgate, and logic circuit.
 16. The method of claim 15, further comprisingcorrecting, with error control circuits, the data read from the selectedmemory address before performing the comparison with incoming data inthe comparison buffer.
 17. The method of claim 15, wherein the storingof the data read from the selected memory address in the comparisonbuffer is performed at the same time as the storing of the incomingdata.
 18. The method of claim 15, wherein reading data already stored atthe selected memory address is performed with sense amplifiers.
 19. Themethod of claim 15, wherein writing data to the selected memory addressis performed by write drivers.
 20. The method of claim 15, wherein thecomparison buffer comprises a multiplexer, a NOR gate, a first Dflip-flop gate, a second D flip-flop gate, and logic circuit.